This invention relates to electronics, in general, and more specifically, to capacitively sensed micromachined components and methods of manufacturing.
Two-chip inertial sensing systems suffer from at least the following two problems. First, two-chip inertial sensing systems have a low signal-to-noise ratio. Second, the electrical interconnection of the two chips in a two-chip inertial sensing system has large parasitic capacitances.
Monolithic inertial sensing systems eliminate the large parasitic capacitances of the two-chip inertial sensing systems. Monolithic inertial sensing systems also have a higher signal-to-noise ratio than the two-chip inertial sensing systems. Monolithic inertial sensing systems, however, typically require lengthy manufacturing processes. Furthermore, monolithic inertial sensing systems require a more complicated passivation scheme that is compatible with both Complementary Metal-Oxide-Semiconductor (CMOS) and Non-Volatile-Memory (NVM) architectures. Furthermore, monolithic inertial sensing systems also require bond-on-electronics capabilities for wafer bonding.
Accordingly, a need exists for a micromachined component and method of manufacture that provides an inertial sensing system with a high signal-to-noise ratio, a short manufacturing process, and minimal or no modifications to existing CMOS manufacturing processes.